IPscreener v3.0

IPscreener API Specification

Version 3.0

General

This is a technical documentation that describes the IPscreener API's interaction with the AutoMatch search engine. The specification is intended for those who are experienced in programming software applications and intend to implement the IPscreener API service. This documentation is subject to continuous change, however normally backward compatibility is maintained.
Disclaimer
The sample method calls, success response and error response in API details are provided for general information purposes only.
The terminology used in this document may differ from other specifications of API's for fetching of data.

Postman shared collection

https://www.getpostman.com/collections/693693d572901418f49d

How to Import Postman collection

Requirments

All our API's requires https (encrypted) connections , do not use http

API Endpoints

GET Index

The Index API is used to retrieve the indexes accessible by a customer by the end client, whereby both the technical description of an index as well as the access number is provided. If no index is specified in the search request, the master index will be used as default. A maximum of three parallel indexes may be accessed in one single IPscreener query this includes customer specific indexes as well. If you are a platform provider, by adding the client-id header you will also see the technical index list available for your respective clients in your platform.

URL: https://api.ipscreener.com/v3/index

Method: GET

Headers:

required: authorization=[value]

authorization: An API authorization key must be sent with all requests. You need to contact the IPscreener support team to get the API authorization key.

Success response:

data: Retrieval of a list of indexes accessible for a specific API authorization key.

Success Response

HTTPS Success Response 200 OK

{
    "status": "success",
    "message": "Resource Fetched Successfully",
    "data": [
        {
            "index-id": "Boost",
            "name": "Boost"
        },
        {
            "index-id": 54523,
            "name": "FTO"
        },
        {
            "index-id": 1,
            "name": "Master"
        }
    ]
}

Error Response

HTTP Status Code: 401 Unauthorized (No API authorization key found)

{
    "message": "No API Key is found in request"
}

HTTP Status Code: 403 Forbidden (Using wrong API authorization key)

{
    "message": "Invalid authentication credentials"
}

HTTP Status Code: 422 Unprocessable entity (When using invalid client-id)

{
    "status": "error",
    "message": "No permission granted for this client-id.",
    "data": null
}

Sample Call (cURL)

curl -X GET \
  https://api.ipscreener.com/v3/index \
  -H 'Authorization: <value>' \

The IPscreener search API

This API receives a text query input and then uses the AutoMatch semantic search engine to retrieve similar results from the worldwide patent database collection. The search procedure includes a first response to a query by returning a session ticket, which then is used to retrieve the results when ready for retrieval. Processing an IPscreeener query typically takes 15-30 seconds, and the patent data is delivered in a JSON format. The number of records delivered depends on the figure specified by the requested-hits parameter and are presented in order of ranked relevance. If the requested-hits parameter is null or absent, 25 records are returned by default. The request procedure is optimized for returning up to 100 records.

If no switches are provided IPscreener will select the most appropriate general settings for carrying out the semantic matching procedure, and returns a single result list. If the query specifies several indexes to be queried in the request, the number of results set by the requested-hits parameter applies to all. Thus, this is the number retrieved for each and one of the queried indexes, where the results for each index are presented sequentially according to the request order in the query string.

POST Search

URL: https://api.ipscreener.com/v3/search

Method: POST

Headers

Required:
authorization=[value]

reference-number=[value]

Body

Required:

query=[string]

Optional:

requested-hits=[positive integer]

view=[bibliographic, claim, description, image, pdf, passage]

index=[positive integer(s) with comma separator or value 'boost']

class=[string]

date=[yyyy-mm-dd]

Header

authorization:An API authorization key must be sent with all requests. You need to contact the IPscreener support team to get the API authorization key.

reference-number: This number is used for tracking the API calls for each client. The same number which is sent as input is returned in the header without any modifications.

Body

query: The text on which the search is performed.

requested-hits: This is the number of relevant hit records which you want to fetch in the result list. If this parameter is not used in the search request, by default 25 records are returned.

view: This input parameter is used to specify the data fields that are required to be returned for each hit in the response. You can specify a combination of fields using comma to separate the values. If this parameter is not used is all data fields except the description field are fetched.

index: This input parameter is used to specify which index will be used in a search.

date (cut-off): This is used to search everything up to this date. Everything after this date will be ignord in a search.

class: This input parameter is used to specify your search to that IPC/CPC class.

The available field parameters are:

bibliographic: (includes Applicant, Inventor, Class, Title and Abstract fields, all sections can return multiple data)

claim: (Covers all the patent claims)

description: (This is the full description, tables and charts are excluded)

image: (Presented in base64 format)

pdf: (An URL link to the PDF API is provided)

passage: (The paragraph within a document that the AutoMatch engine considers to be most relevant)

Success Response:

data: the session ticket value associated with a search request used to GET the search results.

Success Response

Body content format: JSON

The below response will be returned while the request is still being processed.

HTTP Status Code: 202 Accepted

{
    "status": "success",
    "message": "Processing",
    "data": null
}

The below response will be returned once the search request has been processed. To view the result please use the GET search API with the ticket value.

HTTP Status Code: 200 OK

{ 
	"status": "success", 
	"message": "Ticket received", 
	"data": "<ticket value>" 
}

Error Response

HTTP Status Code: 401 Unauthorized (No API authorization key found)

{
	"message": "No API Key is found in request"
}

HTTP Status Code: 403 Forbidden (Using wrong API authorization key)

{
	"message": "Invalid authentication credentials"
}

HTTP Status Code: 403 Forbidden (When the IP restriction is activated and source IP is not whitelisted)

{
	"message": "Your IP address is not allowed"
}

HTTP Status Code: 422 Unprocessable entity BODY

Query:

HTTP Status Code: 422 Unprocessable Entity Query (When null value passed in query parameter)

{
    "status": "error",
    "message": "Query parameter is required and should not be empty.",
    "data": null
}

HTTP Status Code: 422 Unprocessable Entity Query (Text to short/unsupported language/only numbers.)

{
    "status": "error",
    "message": "Can not validate query input language",
    "data": null
}

Reference-number

HTTP Status Code: 422 Unprocessable Entity Reference-number (When null value passed in reference-number parameter)

{
    "status": "error",
    "message": "Reference-number parameter is required and should not be empty or more than 100 characters.",
    "data": null
}

Requested-hits

HTTP Status Code: 422 Unprocessable Entity Requested-hits (When wrong value passed in requested-hits parameter)

{
	"status": "error",
	"message": "The requested hits must be an integer. The requested hits must be at least 1.",
	"data": null
}

HTTP Status Code: 422 Unprocessable Entity Requested-hits (When greater than 100 value passed in requested-hits parameter)

{
	"status": "error",
	"message": "The requested hits may not be greater than 100.",
	"data": null
}

View

HTTP Status Code: 422 Unprocessable Entity View (When wrong value passed in view parameter)

{
	"status": "error",
	"message": "The accepted values for view are: bibliographic, claim, description, image, pdf, passage. The same value may occur once.",
	"data": null
}

Index

HTTP Status Code: 422 Unprocessable Entity Index (When wrong value passed into index parameter)

{
	"status": "error",
	"message": "You do not have permission to this index or index is offline.",
	"data": null
}

HTTP Status Code: 422 Unprocessable Entity Index (When null value passed into index parameter)

{
	"status": "error",
	"message": "You must at least select 1 index.",
	"data": null
}

Date

HTTP Status Code: 422 Unprocessable Entity Date (When entering a incorrect format)

{
    "status": "error",
    "message": "The date is not a valid date.",
    "data": null
}

HTTP Status Code: 422 Unprocessable Entity Date ( If space, enter, tab or blank is used. )

{
    "status": "error",
    "message": "date can not only contain white space, new line, tab or empty input",
    "data": null
}

Class

HTTP Status Code: 422 Unprocessable Entity Class( When input value is incorrect)

{
    "status": "error",
    "message": "Class data is not valid",
    "data": null
}

HTTP Status Code: 422 Unprocessable Entity Class (When whitespace is used as a value in class)

{
    "status": "error",
    "message": "class can not only contain new line, tab or empty input",
    "data": null
}

HTTP Status Code: 429 Too many requests (API rate limit exceeded)

{
	"message": "API rate limit exceeded"
}

HTTP Status Code: 408 Request Timeout (When one or many indexes are offline or having other troubles)

{
	"status": "error",
	"message": "One or more indexes seems to be offline.",
	"data": null
}

Sample Call (cURL)

Sample Call(cURL)

curl -X POST \
  https://api.ipscreener.com/v3/search \
  -H 'Authorization: xxx' \
--data-urlencode 'index=1' \
--data-urlencode 'requested-hits=5' \
--data-urlencode 'view=bibliographic,claim,description,pdf,passage' \
--data-urlencode 'date=2019-12-31' \
--data-urlencode 'class=class=G01F11/261'

GET Search

URL: https://api.ipscreener.com/v3/search

Method: GET

Header:

required:

authorization=[Value]

Body:

required:

ticket=[ticket value, string]

Header:

authorization: An API authorization key must be sent with all requests. You need to contact the IPscreener support team to get the API authorization key.

Body:

ticket: The ticket value used to retrieve the results is the ticket session identification data string received by the POST search request.

Success Response:

index value: After the parameter automatch-result there is an integer value, e.g. index-1. This value indicates the specific index and associated settings used for performing the matching procedure. If several indexes are targeted with a search (maximum three in parallel), each result list will be presented separately, one after the other.

score: The score is the AutoMatch engine indication of the estimated relevance of a document.

position: The position refers to the record number of the hit in the search results, where the search results are sorted on the relevance score value in descending order.

country: This returns a two-letter country code describing the origin of the patent publication.

number: It is the publication number for the application or the granted patent retrieved.

kind-code: The kind codes are used to identify the type of patent publication. More information on this syntax is available at: www.wipo.org. Some of the most common kind codes are:

- A1 - Publ. of Application with search report
- A2 - Publ. of Application without search report
- B1 - Patent publication
- B2 - Patent after modification

family-number: Patent family is a set of interrelated patent applications filed in one or more countries to protect the same invention by inventor(s). Each patent family has a unique number and this value returns that number. Family numbers are provided by EPO according to the Inpadoc specification.

publication-date: The publication date is the date on which a patent application/grant is first published. It is the date on which the document is made available to the public.

bibliographic: The bibliographic data section includes reference data on who is behind the patent application as well as summary data on the content and the technical field.

applicant (array): This field provides information about the patent owner(s) or applicant(s).

name: This field returns the name of the patent owner(s) or applicant(s).

inventor (array): This field provides information about the inventor(s).

name: This field returns the name of the inventor(s).

class (array): The classification scheme is a system of codes that groups inventions according to technical area, where IPC and CPC is the most common. The class information is divided into the follwoing hierarchy, including four sections:

sub: This is the complete class information e.g. H04M15/03.
type: This declares the classification system referred to e.g. IPC, CPC

title (array): This section includes the full title of the patent.

language: The language tag in which the title of patent is written.
text: It is the title text of the patent.

abstract (array): This is the summary describing the essence of the scope of a patent.

language: The language in which the abstract of patent is given.
text: It is the text content of the abstract of the patent.

passage: Shows the paragraph within a document that the AutoMatch engine considered to be most relevant to the query.

section: The section where the relevant paragraph is located
text: The paragraph within a document considered to be most relevant by the engine.
language: The language in which the passage of patent is written.

claim (array): A claim defines exactly what is claimed by the invention and therefore what is sought to be protected. It clearly lays down what the patent does and does not cover.

language: The language in which the claim of patent is written.
text: It is the text content of the claim of the patent.

description (array): The detailed description describes in detail what the invention is and how it is made and used. It reflects the complete picture of the invention.

language: The language in which the description of patent is written.
text: It is the text content of the description of the patent.

image: It contains the first image of the patent document.

data: Image encrypted in Base64 format. This will always be the first image of the patent (if first image exists).

pdf: It provides a PDF API link. This link enables access to download the full PDF document.

Success Response:

Body content format: JSON

The below response will be returned while the request is still being processed.

HTTP Status Code: 202 Accepted

{
    "status": "success",
    "message": "Processing",
    "data": null
}

When checking if data is ready for retrieval you only use the parameter ticket value. The response below will be returned once the search request has been processed and is ready for delivery.

Do note; the response below is an example where we have truncated the data for several fields to make the view more condensed and comprehensive.

HTTP Status Code: 200 OK

{
    "status": "success",
    "message": "Resource Fetched Successfully",
    "data": {
        "ipscreener-results": {
            "index-1": [
                {
                    "relevance": {
                        "score": 209.0604,
                        "position": 1,
                        "country": "US",
                        "number": "9927975",
                        "kind-code": "B2",
                        "family-number": 61071468,
                        "publication-date": "2018-02-08"
                    },
 					"bibliographic": {
                        "applicant": [
                            {
                                "name": "Micron Technology"
                            },
                            {
                                "name": " Inc."
                            }
                        ],
                       "inventor": [
                            {
                                "name": "Pratt Thomas L."
                            }
                        ],
                        "class": [
                            {
                                "sub": "G06F3/0604",
                                "type": "CPC"
                            },
                            {
                                "sub": "G06F3/0605",
                                "type": "CPC"
                            },
                       "title": [
                            {
                                "language": "en",
                                "text": "Hybrid memory drives, computer system, and related method for operating a	 multi-mode hybrid drive"
                            }
                        ],
                        "abstract": [
                            {
                                "language": "en",
                                "text": "A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device...
                           }
                        ]
                    },
                    "passage": {
                        "section": "description",
                        "language": "en",
                        "text": "at a lower price.\nHybrid drives include features of both the SSDs and HDDs in that traditional magnetic HDD storage media is used for long term storage and solid state Flash-type storage media is used for cache storage. Thus, hybrid drives have become desirable because they deliver higher performance than conventional drives, but at a more reasonable cost...
                   },
                    "claim": [
                        {
                            "language": "en",
                            "text": "1. A hybrid memory drive, comprising:\na bulk memory device including:\nbulk storage media including non-volatile memory;\na cache port; and\na first controller operably coupled with the cache port and the bulk storage media; and\na removable cache memory device including:\ncache storage media including non-volatile memory...
                        }
                    ],
                    "description": [
                        {
                            "language": "en",
                            "text": "TECHNICAL FIELD\nThe disclosure, in various embodiments, relates generally to the field of computer systems and mass storage devices. More specifically, the disclosure relates to mass storage devices configured to operate as either a hybrid drive or a stand-alone drive depending on its mode of operation.\nBACKGROUND\nNon-volatile memory is commonly used for mass storage of data, such as within consumer electronic devices...
                        }
                    ],
                    "image": {
                        "data":<base64 format link>
                   },
                    "pdf": "https://api.ipscreener.com/v3/pdf/US-9927975-B2"
                },

Error Response

HTTP Status Code: 204 No Content (When no result could be found)

<blank>

HTTP Status Code: 404 Not Found (When wrong value passed into ticket parameter)

{
    "status": "error",
    "message": "Ticket not found",
    "data": null
}

HTTP Status Code: 404 Not Found (When empty value passed into ticket parameter)

{
    "status": "error",
    "message": "Parameter ticket can not be empty",
    "data": null
}

HTTP Status Code: 429 Too many requests (API rate limit exceeded)

{
	"message": "API rate limit exceeded"
}

Sample Call (cURL)

Sample Call (cURL)

curl -X GET \
  'http://api.ipscreener.com/v3/search?ticket=<value>' \
  -H 'Authorization: xxx' \

GET Stats

URL: https://api.ipscreener.com/v3/stats

Method: GET

Headers:

required: authorization=[value]

authorization: An API authorization key must be sent with all requests. You need to contact the IPscreener support team to get the API authorization key.

Body:

ticket: The ticket value used to retrieve the results is the ticket session identification data string received by the POST search request.

Success Response:

publication years (array): What year the patent was first published.

applicants (array): Who made the application.

classes (array): Which classes are used in the search.

priority country (array): Which country does the most applications.

terms (array): The most relevant keywords based on quary.

value (array): The score is the AutoMatch engine indication of the estimated relevance of a document.

Success Response

Body content format: JSON

The below response will be returned while the request is still being processed.

HTTP Status Code: 202 Accepted

{
    "status": "success",
    "message": "Processing",
    "data": null
}

The below response will be returned once the search request has been processed. To view the result please use the GET search API with the ticket value.

HTTP Status Code: 200 OK

{
    "status": "success",
    "message": "Resource Fetched Successfully",
    "data": {
        "ipscreener-results": {
            "index-1": {
                "publication_years": [
                    {
                        "publication_year": 1992,
                        "value": 9
                    },
                    {
                        "publication_year": 2013,
                        "value": 5
					}      
                ],
                "applicants": [
                    {
                        "name": "ROBBINS EDWARD S III",
                        "value": 9
                    },
                    {
                        "name": "LOGIDOS APS",
                        "value": 4
                    }
                ],
                "classes": [
                    {
                        "main": "G01F11",
                        "value": 86
                    },
                    {
                        "main": "B65D83",
                        "value": 22
                    }
                ],
                "priority_country": [
                    {
                        "country": "US",
                        "value": 44
                    },
                    {
                        "country": "CA",
                        "value": 5
                    }

                ],
                "terms": [
                    {
                        "name": "ssds",
                        "value": 5.593044
                    },
                    {
                        "name": "cells",
                        "value": 3.1091845
                    }
                ]
            }
        }
    }
}

HTTP Status Code: 204 No Content (When no result could be found)

<Blank>

Error Response

HTTP Status Code: 401 Unauthorized (No API authorization key found)

{
    "message": "No API Key is found in request"
}

HTTP Status Code: 403 Forbidden (Using wrong API authorization key)

{
    "message": "Invalid authentication credentials"
}

Sample Call (cURL)

curl -X GET \
  https://api.ipscreener.com/v3/stats \
  -H 'Authorization: xxx' \

GET pdf

The PDF API is used to retrieve the original patent document(s) corresponding to a search query. From the requested patent number input via an URL query, the API request returns a PDF file in base64 format.

URL: https://api.ipscreener.com/v3/pdf/patent-number

Method: GET

Headers:

authorization: An API authorization key must be sent with all requests. You need to contact the IPscreener support team to get the API authorization key.

Parameters:

patent-number: This descriptor represents uniquely a patent publications. The full patent number is based on a country code, a number and a kind code, separated with hyphens, e.g. US-2006258329-A1. The format of the patent number must be DocDB.

data: Retrieval of a complete PDF document encoded in Base64 format.

Success Response

HTTP Status Code: 200 OK

{ 
	"status": "success", 
	"message": "Resource Fetched Successfully.", 
	"data":"<Complete PDF document encoded in Base64 format>" 
 }

Error Response

HTTP Status Code: 401 Unauthorized (No API authorization key found)

{
	"message": "No API Key is found in request"
}

HTTP Status Code: 403 Forbidden (Using wrong API authorization key)

{
	"message": "Invalid authentication credentials."
}

HTTP Status Code: 403 Forbidden (When the IP restriction is activated and source IP is not whitelisted)

{
	"message": "Your IP address is not allowed."
}

HTTP Status Code: 404 Not found (PDF is not available)

{ 
	"status": "error", 
	"message": "The requested url or its parameters are wrong.", 
	"data": null 
 }

HTTP Status Code: 422 Unprocessable entity (When null value passed in patent-number parameter)

{
	"status": "error",
	"message": "Patent-number parameter should not be empty.",
	"data": null
}

HTTP Status Code: 429 Too many requests (API rate limit exceeded)

{
	"message": "API rate limit exceeded"
}

Sample Call (cURL)

Sample Call (cURL)

curl -X GET \
  'https://api.ipscreener.com/v3/pdf/<Patent number>' \
  -H 'Authorization: xxx' \

API Code Examples

API Examples

POST Search

POST Request

curl --location --request POST 'https://api.ipscreener.com/v3/search' \
--header 'Authorization: <Key>' \
--header 'Reference-number: SE-123' \
--header 'Content-Type: application/x-www-form-urlencoded' \
--data-urlencode 'query=A solid-state drive (SSD) is a solid-state storage device that uses integrated circuit assemblies as memory to store data persistently, typically using flash memory. It is also sometimes called a solid-state device or a solid-state disk,[1] although SSDs lack the physical spinning disks and movable read-write heads used by the conventional electromechanical storage such as hard drives ("HDD") or floppy disks.[2]

Compared with the electromechanical drives, SSDs are typically more resistant to physical shock, run silently, and have quicker access time and lower latency.[3] SSDs store data in semiconductor cells. As of 2019, cells can contain between 1 and 4 bits of data. SSD storage devices vary in their properties according to the number of bits stored in each cell, with single bit cells ("SLC") being generally the most reliable, durable, fast, and expensive type, compared with 2 and 3 bit cells ("MLC" and "TLC"), and finally quad bit cells ("QLC") being used for consumer devices that do not require such extreme properties and are the cheapest of the four. In addition, 3D XPoint memory (sold by Intel under the Optane brand), stores data by changing the electrical resistance of cells instead of storing electrical charges in cells, and SSDs made from RAM can be used for high speed, when data persistence after power loss is not required, or may use battery power to retain data when its usual power source is unavailable.[4] Hybrid drives or solid-state hybrid drives (SSHDs), such as Apple'\''s Fusion Drive, combine features of SSDs and HDDs in the same unit using both flash memory and a HDD in order to improve the performance of frequently-accessed data.[5][6][7]' \
--data-urlencode 'index=1' \
--data-urlencode 'requested-hits=2' \
--data-urlencode 'view=bibliographic,claim,description,pdf,passage' \
--data-urlencode 'date=2019-12-31'

POST Recive

{
    "status": "success",
    "message": "Ticket received",
    "data": "<value>"
}

GET Search

GET Search Request
curl --location --request GET 'http://api.ipscreener.com/v3/search?ticket=<value>' \ --header 'Authorization: <Key>'
GET Search Recive
{ "status": "success", "message": "Resource Fetched Successfully", "data": { "ipscreener-results": { "index-1": [ { "relevance": { "score": 207.60657, "position": 1, "country": "US", "number": "2019102102", "kind-code": "A1", "family-number": 65896641, "publication-date": "2019-04-04" }, "bibliographic": { "applicant": [ { "name": "INTEL CORPORATION" } ], "inventor": [ { "name": "NATARAJAN" }, { "name": " Shankar" }, { "name": "MADRASWALA" }, { "name": " Aliasgar S." } ], "class": [ { "sub": "G06F3/0647", "type": "CPC" }, { "sub": "G06F3/0613", "type": "CPC" }, { "sub": "G06F3/0649", "type": "CPC" }, { "sub": "G06F3/0679", "type": "CPC" }, { "sub": "G06F3/068", "type": "CPC" }, { "sub": "G06F11/1072", "type": "CPC" }, { "sub": "G11C11/5621", "type": "CPC" }, { "sub": "G11C11/5628", "type": "CPC" }, { "sub": "G11C16/0483", "type": "CPC" }, { "sub": "G11C2211/5622", "type": "CPC" }, { "sub": "G11C2211/5641", "type": "CPC" }, { "sub": "G06F3/06", "type": "IPC" } ], "title": [ { "language": "en", "text": "METHOD, SYSTEM, AND APPARATUS FOR IMPROVING BANDWIDTH OF STORAGE DEVICES" } ], "abstract": [ { "language": "en", "text": "A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed." } ] }, "passage": { "section": "description", "language": "en", "text": "BACKGROUND\nA solid state drive (SSD) is a data storage device that uses integrated circuit assemblies as memory to store data persistently. SSDs have no moving mechanical components and this distinguishes SSDs from traditional electromechanical magnetic disks, such as, hard disk drives (HDDs) or floppy disks, which contain spinning disks and movable read/write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, run silently, have lower access time, and less latency. Many types of SSDs use NAND-based flash memory which comprises an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed.\nNAND-based flash memory stores information (i.e., data) in individual memory cells. In single-level cell (SLC) NAND flash technology, each memory cell may exist in one of two voltage states, storing one bit of information per memory cell. A multi-level cell (MLC) is a memory cell capable of storing more than" }, "claim": [ { "language": "en", "text": "1. A method, comprising:\ndetermining that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media;\ncopying a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media;\nconcurrently with the copying of the first subset of the plurality of pages, copying a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; and\ndetermining that the copying of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copying of the first subset of the plurality of pages and the second subset of the plurality of pages.\n2. The method of claim 1, wherein the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein copying of the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media comprises:\ncopying the fourth page from the first type of storage media to the second type of storage media, in response to determining that the third page has already been copied from the first type of storage media to the second type of storage media.\n3. The method of claim 1, the method further comprising:\ncopying the data from the first type of storage media to a set of latches of the non-volatile memory;\nsubsequent to copying the data from the first type of storage media to the set of latches of the non-volatile memory, copying the data from the set of latches to the second type of storage media via operations comprising:\nswitching from a first mode to a second mode using a first set feature command;\nissuing a second feature set command to specify a destination write mode; and\nissuing a program opcode to program the second type of storage media.\n4. The method of claim 1, the method further comprising:\nissuing a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and\nissuing a program opcode to program the second type of storage media.\n5. The method of claim 1, wherein the data is moved from the first type of storage media to the second type of storage media without generating an intermediate copy outside of the non-volatile memory.\n6. The method of claim 1, wherein on an average, I/O operations to the first type of storage media are performed faster in comparison to I/O operations to the second type of storage media, wherein the non-volatile memory has fewer blocks configured as the first type of storage media in comparison to the second type of storage media, and wherein data has to be moved periodically from the first type of storage media to the second type of storage media to conserve space in the first type of storage media.\n7. The method of claim 1, wherein the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is quad-level cell (QLC) NAND.\n8. The method of claim 1, wherein the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is multi-level cell (MLC) NAND.\n9. A non-volatile memory device, comprising:\na non-volatile memory; and\na controller coupled to the non-volatile memory, wherein the controller is operable to:\ndetermine that data has to be moved internally within the non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media;\ncopy a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media;\ncopy a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media, concurrently with the copy of the first subset of the plurality of pages; and\ndetermine that the copy of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copy of the first subset of the plurality of pages and the second subset of the plurality of pages.\n10. The non-volatile memory device of claim 9, wherein the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein the controller to copy the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media is to:\ncopy the fourth page from the first type of storage media to the second type of storage media, in response to a determination that the third page has already been copied from the first type of storage media to the second type of storage media.\n11. The non-volatile memory device of claim 9, wherein the controller is further operable to:\ncopy the data from the first type of storage media to a set of latches of the non-volatile memory;\nsubsequent to the copy of the data from the first type of storage media to the set of latches of the non-volatile memory, copy the data from the set of latches to the second type of storage media via operations performed to:\nswitch from a first mode to a second mode using a first set feature command;\nissue a second feature set command to specify a destination write mode; and\nissue a program opcode to program the second type of storage media.\n12. The non-volatile memory device of claim 9, wherein the controller is further operable to:\nissue a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and\nissue a program opcode to program the second type of storage media.\n13. The non-volatile memory device of claim 9, wherein the controller is further operable to: cause the data to be moved from the first type of storage media to the second type of storage media without generation of an intermediate copy outside of the non-volatile memory.\n14. The non-volatile memory device of claim 9, wherein on an average, I/O operations to the first type of storage media are performed faster in comparison to I/O operations to the second type of storage media, wherein the non-volatile memory has fewer blocks configured as the first type of storage media in comparison to the second type of storage media, and wherein data has to be moved periodically from the first type of storage media to the second type of storage media to conserve space in the first type of storage media.\n15. The non-volatile memory device of claim 9, wherein the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is quad-level cell (QLC) NAND.\n16. The non-volatile memory device of claim 9, wherein the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is multi-level cell (MLC) NAND.\n17. A system, comprising:\na display;\na non-volatile memory device comprising a non-volatile memory; and\na controller coupled to the non-volatile memory, wherein the controller is operable to:\ndetermine that data has to be moved internally within the non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media;\ncopy a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media;\ncopy a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media, concurrently with the copy of the first subset of the plurality of pages; and\ndetermine that the copy of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copy of the first subset of the plurality of pages and the second subset of the plurality of pages.\n18. The system of claim 17, wherein the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein the controller to copy the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media is to:\ncopy the fourth page from the first type of storage media to the second type of storage media, in response to a determination that the third page has already been copied from the first type of storage media to the second type of storage media.\n19. The system of claim 17, wherein the controller is further operable to:\ncopy the data from the first type of storage media to a set of latches of the non-volatile memory;\nsubsequent to the copy of the data from the first type of storage media to the set of latches of the non-volatile memory, copy the data from the set of latches to the second type of storage media via operations performed to:\nswitch from a first mode to a second mode using a first set feature command;\nissue a second feature set command to specify a destination write mode; and\nissue a program opcode to program the second type of storage media.\n20. The system of claim 17, wherein the controller is further operable to:\nissue a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and\nissue a program opcode to program the second type of storage media." } ], "description": [ { "language": "en", "text": "BACKGROUND\nA solid state drive (SSD) is a data storage device that uses integrated circuit assemblies as memory to store data persistently. SSDs have no moving mechanical components and this distinguishes SSDs from traditional electromechanical magnetic disks, such as, hard disk drives (HDDs) or floppy disks, which contain spinning disks and movable read/write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, run silently, have lower access time, and less latency. Many types of SSDs use NAND-based flash memory which comprises an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed.\nNAND-based flash memory stores information (i.e., data) in individual memory cells. In single-level cell (SLC) NAND flash technology, each memory cell may exist in one of two voltage states, storing one bit of information per memory cell. A multi-level cell (MLC) is a memory cell capable of storing more than a single bit of information. For example, a MLC NAND flash memory that has sixteen possible voltage states per memory cell may store four bits of information per memory cell, and may be referred to as a quad-level cell (QLC) NAND.\nBRIEF DESCRIPTION OF THE DRAWINGS\nReferring now to the drawings in which like reference numbers represent corresponding parts throughout:\nFIG. 1 illustrates a block diagram of a computing environment in which a host is coupled to a SSD comprised of NAND memory configured into SLC and QLC blocks, in accordance with certain embodiments;\nFIG. 2 illustrates a block diagram that shows how blocks of the NAND memory may be written in SLC mode or in QLC mode, in accordance with certain embodiments;\nFIG. 3 illustrates a block diagram that shows an existing NAND command set and extensions to the NAND command set, in accordance with certain embodiments;\nFIG. 4 illustrates a block diagram that shows how four pages of SLC blocks are mapped to a single page of QLC blocks, in accordance with certain embodiments;\nFIG. 5 illustrates a block diagram that shows how QLC programming is performed in two steps, in accordance with certain embodiments;\nFIG. 6 illustrates a flowchart that shows how data is moved from SLC NAND to QLC NAND by using an existing NAND command set, in accordance with certain embodiments;\nFIG. 7 illustrates a flowchart that shows how data is moved from SLC NAND to QLC NAND via internal latches, in accordance with certain embodiments;\nFIG. 8 illustrates a flowchart that shows how data is moved from SLC NAND to QLC NAND via a new set feature command for internal data copy, in accordance with certain embodiments;\nFIG. 9 illustrates a flowchart that shows how data is moved from SLC NAND to QLC NAND, in accordance with certain embodiments; and\nFIG. 10 illustrates a block diagram of a system, in accordance with certain embodiments.\nDETAILED DESCRIPTION\nIn the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made.\nCertain SSDs may be configured such that the NAND memory of a SSD is configured into SLC blocks and QLC blocks. The SLC blocks may comprise relatively faster media in comparison to the QLC blocks that may comprise relatively slower media. Reads and writes to the relatively faster media may be performed relatively faster in comparison to reads and writes to the relatively slower media. Since there is a relatively small amount of SLC blocks in comparison to the amount of QLC blocks, the firmware of the SSD may periodically copy data from the relatively faster SLC blocks to the relatively slower QLC blocks, so that the data storage space provided by the SLC blocks is prevented from getting completely filled up.\nThe copying of data from the SLC blocks to the QLC blocks may be performed by reading the data out from SLC blocks to Application-Specific Integrated circuit (ASIC) Static Random Access Memory (SRAM) located in the controller of the SSD, and then writing the data back from the ASIC SRAM to the QLC blocks, or by internally moving the data within the NAND memory from the SLC blocks to the QLC blocks. Internally moving the data within the NAND memory from the SLC blocks to the QLC blocks provides significant write bandwidth improvement over reading the data out from the SLC blocks to ASIC SRAM, and then writing the data back from the ASIC SRAM to QLC blocks, by avoiding the input/output (I/O) of data from and to the NAND memory.\nCertain embodiments provide mechanisms in which a NAND memory in a SSD is configured into SLC blocks and QLC blocks, and internal data movements are performed from SLC blocks to QLC blocks. As a result, the write bandwidth of the SSD increases in comparison to situations in which data is read out from SLC blocks to the controller of the SSD, and then the data written from the controller of the SSD to QLC blocks.\nFIG. 1 illustrates a block diagram of a computing environment 100 in which a host 102 is coupled to a SSD 104, in accordance with certain embodiments. The SSD 104 may be comprised of a controller 106 and a NAND complex 108. The NAND complex 108 may also be referred to as a non-volatile memory complex that is comprised of a plurality of non-volatile memory modules that are directly or indirectly coupled, i.e., the non-volatile memory modules that are directly or indirectly coupled form a complex that is referred to as a non-volatile memory complex.\nIn certain embodiments, the NAND complex 108 may be comprised of a plurality of NAND memory 110 that may form a NAND array. In certain embodiments the NAND complex 108 may be a multi-level cell (MLC) NAND (e.g., such as a triple-level cell (TLC) NAND or a quad-level cell (QLC) NAND) or any other type of NAND or any other type of non-volatile memory complex, where each of the memory cells of the NAND complex 108 in the SSD 104 may store more than 1 bit of information. In other embodiments, the SSD 104 may be comprised of a controller 106 that controls certain other types of non-volatile memory, such as NOR memory or some other suitable non-volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium. Nonlimiting examples of nonvolatile memory may include any or a combination of: solid state memory [such as planar or three Dimensional (3D) NAND flash memory or NOR flash memory], 3D crosspoint memory, storage devices that use chalcogenide phase change material (e.g., chalcogenide glass), byte addressable nonvolatile memory devices, multi-threshold level NAND flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), other various types of non-volatile random access memories (RAMs), magnetic storage memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device. In some embodiments, 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of words lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. A memory device may refer to the die itself and/or to a packaged memory product. In certain embodiments, a memory module with non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standard (the JEDEC standards cited herein are available at www.jedec.org). In certain embodiments, the SSD 104 may be capable of storing several terabytes of data or more.\nIn certain embodiments, the NAND memory 110 is configurable into SLC blocks 112 and QLC blocks 114 by the controller 106 of the SSD 104. The SLC blocks 112 appear as SLC NAND and the QLC blocks 114 appear as QLC NAND for storage of data. In certain embodiments, the controller 106 of the SSD 104 may include firmware 116 that implements a controller application 118, where the controller application 118 configures the NAND memory 110 into the SLC blocks 112 and the QLC blocks 114.\nIn certain embodiments, the host 102 may be comprised of any suitable computational device, such as a personal computer, a mainframe, a telephony device, a smart phone, a storage controller, a blade computer, a processor with memory, etc. In certain embodiments, the host 102 may communicate with the SSD 104 over a bus (such as a Peripheral Component Interconnect (PCIe), Serial Advanced Technology Attachment (SATA), Serial Attached Small Computer System Interface (SAS)) or a network, such as the Internet, a storage area network (SAN), a local area network (LAN), etc. In certain embodiments, the host 102 may communicate with the SSD 104 over a Non-Volatile Memory Express (NVMe) interface (http://www.nvmexpress.org).\nIn certain embodiments, the controller application 118 (implemented in firmware as shown in FIG. 1, or implemented in other embodiments via firmware, software, hardware or any combination thereof) that executes in the controller 106 of the SSD 104 programs the memory cells of the NAND memory 110. The SSD 104 also receives commands from the host 102, and then the controller application 118 executes the read and/or write with respect to the NAND complex 108 by converting the read and/or write commands received from the host 102 into memory operations. The controller 106 and the controller application 118 may be implemented in ASIC and/or firmware, software, or any combination thereof.\nThe SSD 104 may also include latches 120 that may comprise devices that may be in a plurality of states, where the latches 120 may be used for temporary storage of data in the SSD 104.\nTherefore, FIG. 1 illustrates certain embodiments in which the controller application 118 configures the NAND memory 110 into SLC blocks 112 and QLC blocks 114, and moves data from SLC blocks 112 to QLC blocks 114 as needed, for conserving the limited storage space provided by the SLC blocks 112 in comparison to the larger storage space provided by the QLC blocks 114.\nFIG. 2 illustrates a block diagram that shows how blocks of the NAND memory 110 may be written in SLC mode or in QLC mode, in accordance with certain embodiments.\nThe controller application that executes in the SSD 104 may configure the NAND memory 110 into a plurality of blocks 200, 202, where a block is a sequence of bits or bytes having a maximum length that is referred to as a block size. A whole block of data is read or written at a time.\nEach of the blocks 200, 202 of the NAND memory 110 may be configured in a SLC mode or in a QLC mode as shown via reference numerals 204, 206. A block that is configured in a SLC mode stores 1 bit of data per memory cell, whereas a block that is configured in a QLC mode stores 4 bits of data per memory cell. I/O operations to blocks configured in the SLC mode may be performed relatively faster in comparison to the I/O operations to blocks configured in the QLC mode. Therefore, blocks in the SLC mode may be used for high bandwidth writes, whereas blocks in the QLC mode made be used for low bandwidth writes and the SLC mode may be referred to as a fast mode and the QLC mode may be referred to as a slow mode. However, the number of blocks configured in the SLC mode is relatively small in comparison to the number of blocks configured in the QLC mode. There may be a maximum limit on the number of blocks that may be configured in the SLC mode. The blocks configured in the SLC mode may be referred to as SLC blocks (as shown via reference numeral 112 in FIG. 1) and the blocks configured in the QLC mode may be referred to as QLC blocks (as shown via reference numeral 114 in FIG. 1).\nIn certain embodiments, if the limited number blocks configured in the SLC mode are close to being full then the data in some of the blocks configured in the SLC mode are moved to some of the blocks configured in the QLC mode. The movement of the data from the SLC blocks 112 to the QLC blocks 114 may also be performed periodically or as needed.\nFIG. 3 illustrates a block diagram 300 that shows an existing NAND command set 302 and certain extensions to the NAND command set (the extensions are shown via reference numerals 304, 306), in accordance with certain embodiments.\nThe existing NAND command set 302 may be comprised of a “set feature” command 308 (also referred to as “set features” command) and other commands 310, where the set feature command 308 and the other commands 310 are described in the publication “Open NAND Flash Interface Specification,” Revision 4.0, published Apr. 2, 2014, by the ONFI Workgroup, where further details of the ONFI workgroup are available at www.onfi.org. The set feature command 308 may be regarded as an Application Programming Interface (API) to modify the settings of a particular feature of the SSD 104.\nIn certain embodiments, the controller application 118 uses the set feature command 308 for internal data movements from SLC blocks 112 to the QLC blocks 114. In other embodiments, a first extension to the existing NAND command set may comprise a first new set feature command 304 to copy from the latches 120 to the QLC blocks 114 and the first new set feature command 304 may be used for internal data movements from SLC blocks 112 to the QLC blocks 114. In certain other embodiments, a second extension to the existing NAND command set may comprise a second new set feature command 306 to copy data directly from the SLC blocks 112 to the QLC blocks 114.\nFIG. 4 illustrates a block diagram 400 that shows how four pages of SLC blocks 112 are mapped to a single page of QLC blocks 114, in accordance with certain embodiments.\nMemory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell. In certain embodiments, a memory cell that is encoded to store a plurality of bits may form a part of a plurality of different pages, with each bit of the memory cell corresponding to a different page. For example, for a memory cell that is encoded with four bits (i.e., memory cells in QLC blocks 114), one bit may correspond to a lower page (LP), another bit may correspond to an upper page (UP), another bit may correspond to an extra page (XP), and another bit may correspond to a top page (TP). Each page (e.g., LP, UP, XP, or TP) may comprise an aggregation of corresponding bits stored by a plurality of different cells of a wordline.\nIn certain embodiments, a plurality of memory cells may comprise a memory cell unit. In the SLC blocks 112 each wordline has 1 page, wherein in the QLC blocks 114 each wordline has 4 pages. For example, in FIG. 4, in the SLC blocks 112, for memory cell units numbered 0, 1, 2, 3, a first page, a second page, a third page, and a fourth page are shown via reference numerals 402, 404, 406, 408. Also, in FIG. 4, in the QLC blocks 114, for a memory cell unit numbered 0, four pages referred to as LP, UP, XP, TP are shown via reference numerals 410, 412, 414, 416, where LP, UP, XP, TP are all addressable by the same wordline.\nTherefore, in FIG. 4, pages that reside on four different memory cell units of the SLC blocks 112 are all mapped into the same memory cell unit of the QLC blocks 114. In certain embodiments, the controller application 118 reads four different memory cell units of the SLC blocks 112 and writes them to a single memory cell unit of the QLC blocks 114. Thus 4 wordlines of SLC blocks 112 are mapped to a single wordline of the QLC blocks 114.\nFIG. 5 illustrates a block diagram 500 that shows how QLC programming is performed in two steps, in accordance with certain embodiments. QLC programming refers to the writing of data to the QLC blocks 114.\nIn certain embodiments, in a first step 502, data is copied to LP, UP, and XP of a memory cell unit of a QLC block 114. In the second step 504 which is performed independently (as shown via reference numeral 506) of the first step 502 for each wordline (i.e., the first step 502 and the second step 504 may be performed in parallel), data is copied to the TP of the memory cell unit of the QLC block 114, where the copying of data to the XP has to be completed prior to copying of data to the TP.\nFIG. 6 illustrates a flowchart 600 that shows how data is moved from SLC NAND (i.e., SLC blocks 112) to QLC NAND (i.e., QLC blocks 114) by using an existing NAND command set 302, in accordance with certain embodiments. The operations shown in FIG. 6 may be performed by the controller application 118 that executes in the controller 106 of the SSD 104, and the operations move data from SLC NAND to QLC NAND without copying data to SRAM that may be present in the controller 106, i.e., internal data movements are performed within the NAND memory 110 to move data from SLC blocks 112 to QLC blocks 114 without transferring the data to the SRAM of the controller 106.\nControl starts at block 606 in which the NAND memory 110 is in the QLC mode. Control proceeds to block 608 in which the controller application 118 determines whether a data move is needed from the SLC blocks 112 to the QLC blocks 114. If so (“Yes” branch 610) control proceeds to block 612 in which the controller application 118 switches the NAND memory 110 to SLC mode using the existing “set feature” command 308. The controller application 118 issues (at block 614) a read command from an SLC block 112 to read LP or UP or XP or TP (i.e., a page is read from the SLC NAND where the page will eventually be copied to one of LP, UP, XP, or TP of a memory cell unit of a QLC NAND), and then switches (at block 616) the NAND memory 110 to the QLC mode by using the existing “set feature” command 308. The controller application 118 then issues (at block 618) a “copy back” command to copy a single page data into a QLC page.\nFrom block 618, control proceeds in to block 620 in which the controller application 118 determines whether the QLC 1st step 502 or QLC 2nd step 504 programming is in progress. Since the QLC 1st step 502 and QLC 2nd step 504 programming are performed independently of each other, control may proceed via branches 622 (2nd step) and 624 (1st step) to blocks 626 and 628 respectively.\nAt block 626, the controller application 118 determines whether TP and XP have been copied, and if so (“Yes” branch 630) control proceeds to block 632 in which the controller application 118 determines whether both 1st step and 2nd step programming have been completed for each row. At block 628, the controller application 118 determines whether LP, UP, and XP have been copied, and if so (“Yes” branch 634) control proceeds to block 632 in which the controller application 118 determines whether both 1st step and 2nd step programming have been completed for each row.\nIf at block 632, the controller application 118 determines that both 1st step and 2nd step programming have been completed for each row (“Yes” branch 636) then the process ends (at block 638). If at block 632, the controller application 118 determines that both 1st step and 2nd step programming have not been completed for each row (“No” branch 640) then control returns to block 620.\nIf at block 626, the controller application 118 determines that TP and XP have not been copied (“No” branch 642) then control returns to block 612. Additionally, if at block 628, the controller application 118 determines that LP, UP, and XP have not been copied (“No” branch 644) then control returns to block 612.\nIf at block 608, the controller application 118 determines that a data move is not needed from the SLC blocks 112 to the QLC blocks 114 (“No” branch 646) then the process ends (at block 648).\nTherefore, FIG. 6 illustrates certain embodiments in which data is moved from SLC blocks to QLC blocks by using the existing “set feature” command 308 of the existing NAND command set 302.\nFIG. 7 illustrates a flowchart 700 that shows how data is moved from SLC NAND to QLC NAND via internal latches, in accordance with certain embodiments. The operations shown in FIG. 7 may be performed by the controller application 118 that executes in the controller 106 of the SSD 104.\nControl starts at block 706 in which the NAND memory 110 is in the QLC mode. Control proceeds to block 708 in which the controller application 118 determines whether a data move is needed from the SLC blocks 112 to the QLC blocks 114. If so (“Yes” branch 710) control proceeds to block 712 in which the controller application 118 switches the NAND memory 110 to SLC mode using the existing “set feature” command 308. The controller application 118 issues (at block 714) a read command from an SLC block 112 to read LP or UP or XP or TP, and then uses (at block 716) the existing “set feature” command 308 to move data between NAND internal latches (i.e., data is copied from SLC blocks 112 to the latches 120).\nFrom block 716 control proceeds in to block 720 in which the controller application 118 determines whether the QLC 1st step 502 or QLC 2nd step 504 programming is in progress. Since the QLC 1st step 502 and QLC 2nd step 504 programming are performed independently of each other, control may proceed via branches 722 (2nd step) and 724 (1st step) to blocks 726 and 728 respectively.\nAt block 726, the controller application 118 determines whether TP and XP have been copied, and if so (“Yes” branch 730) control proceeds to block 732 in which the controller application 118 determines whether both 1st step and 2nd step programming have been completed for each row. At block 728, the controller application 118 determines whether LP, UP, and XP have been copied, and if so (“Yes” branch 734) control proceeds to block 732 in which the controller application 118 determines whether both 1st step and 2nd step programming have been completed for each row.\nIf at block 732, the controller application 118 determines that both 1st step and 2nd step programming have been completed for each row (“Yes” branch 736) then the controller application 118 switches (at block 738) the NAND memory 110 to QLC mode using the existing “set feature” command 308. The controller application 118 issues (at block 740) a first new NAND set feature command 304 (e.g., via an API) to specify a destination write mode (i.e., a 1st step or 2nd step program). Then, the controller application 118 issues (at block 742) a QLC program opcode that copies data from the internal latches 120 to the QLC blocks 114, and the process ends (at block 743). If at block 732, the controller application 118 determines that both 1st step and 2nd step programming have not been completed for each row (“No” branch 737) then control returns to block 720.\nIf at block 726, the controller application 118 determines that TP and XP have not been copied (“No” branch 744) then control returns to block 712. Additionally, if at block 728, the controller application 118 determines that LP, UP, and XP have not been copied (“No” branch 746) then control returns to block 712.\nIf at block 708, the controller application 118 determines that a data move is not needed from the SLC blocks 112 to the QLC blocks 114 (“No” branch 748) then the process ends (at block 750).\nTherefore, FIG. 7 illustrates certain embodiments in which data is moved from SLC blocks to QLC blocks by using internal latches 120.\nFIG. 8 illustrates a flowchart 800 that shows how data is moved from SLC NAND to QLC NAND via a new set feature command for internal data copy, in accordance with certain embodiments. The operations shown in FIG. 8 may be performed by the controller application 118 that executes in the controller 106 of the SSD 104.\nControl starts at block 806 in which the NAND memory 110 is in the QLC mode. Control proceeds to block 808 in which the controller application 118 determines whether a data move is needed from the SLC blocks 112 to the QLC blocks 114. If so (“Yes” branch 810), then control proceeds to block 812 in which the controller application 118 issues a second new NAND set feature command 306 (e.g., via API) to specify source address (block number and page of SLC address is source address) and destination (QLC address is destination address by default) write mode to specify 1st step or 2nd step programming. Then the controller application 118 issues (at block 814) a QLC program opcode to perform the internal copying of data directly from SLC blocks 112 to the QLC blocks 114, and the process ends (at block 816).\nIf at block 808, the controller application 118 determines that a data move is not needed (“No” branch 818) from the SLC blocks 112 to the QLC blocks 114, then the process end (at block 820).\nTherefore, FIG. 8 illustrates certain embodiments in which data is moved from SLC NAND to QLC NAND via a new set feature command (i.e., the second new set feature command 306) for internal data copy. The second new set feature command 306 takes the SLC address as source, the QLC address as destination and performs the data move operation internally.\nFIG. 9 illustrates a flowchart 900 that shows how data is moved from SLC NAND to QLC NAND, in accordance with certain embodiments. The operations shown in FIG. 9 may be performed by the controller application 118 that executes in the controller 106 of the SSD 104.\nControl starts at block 902 in which a determination is made that data has to be moved internally within a non-volatile memory complex 108 from a plurality of pages of a first type of storage media 112 (e.g., SLC block 112) to a page of a second type of storage media 114 (e.g., QLC blocks 114). A first subset (e.g., LP, UP, XP) of the plurality of pages is copied (at block 904) from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset (e.g., TP) of the plurality of pages is copied (at block 906) from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset of the plurality of pages and the second subset of the plurality of pages, it is determined (at block 908) that the copying of the data from the first type of storage media to the second type of storage media has completed.\nTherefore, FIGS. 1-9 illustrate certain embodiments for copying data from blocks configured in a SLC mode to blocks configured in a QLC mode.\nThe embodiments shown in FIGS. 1-9 have been described for QLC NAND devices using specific types of write mechanisms. However, in alternative embodiments, other types of write mechanisms may be used for QLC NAND devices or for TLC NAND or for MLC NAND devices.\nThe described operations may be implemented as a method, apparatus or computer program product using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “computer readable storage medium”, where a processor may read and execute the code from the computer readable storage medium. The computer readable storage medium includes at least one of electronic circuitry, storage materials, inorganic materials, organic materials, biological materials, a casing, a housing, a coating, and hardware. A computer readable storage medium may comprise, but is not limited to, a magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), Solid State Devices (SSD), etc. The code implementing the described operations may further be implemented in hardware logic implemented in a hardware device (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.). Still further, the code implementing the described operations may be implemented in “transmission signals”, where transmission signals may propagate through space or through a transmission media, such as an optical fiber, copper wire, etc. The transmission signals in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The program code embedded on a computer readable storage medium may be transmitted as transmission signals from a transmitting station or computer to a receiving station or computer. A computer readable storage medium is not comprised solely of transmission signals. Those skilled in the art will recognize that many modifications may be made to this configuration, and that the article of manufacture may comprise suitable information bearing medium known in the art.\nComputer program code for carrying out operations for aspects of the certain embodiments may be written in any combination of one or more programming languages. Blocks of the flowchart and block diagrams may be implemented by computer program instructions.\nFIG. 10 illustrates a block diagram of a system 1000 that includes both the host 102 (the host 102 comprises at least a processor) and the solid state drive 104, in accordance with certain embodiments. For example, in certain embodiments the system 1000 may be a computer (e.g., a laptop computer, a desktop computer, a tablet, a cell phone or any other suitable computational device) that has the host 102 and the solid state drive 104 both included in the system 1000. For example, in certain embodiments the system 1000 may be a laptop computer that includes the solid state drive 104. The system 1000 may include a circuitry 1002 that may in certain embodiments include at least a processor 1004. The system 1000 may also include a memory 1006 (e.g., a volatile memory device), and storage 1008. The storage 1008 may include the solid state drive 104 or other drives or devices including a non-volatile memory device (e.g., EEPROM, ROM, PROM, flash, firmware, programmable logic, etc.). The storage 1008 may also include a magnetic disk drive, an optical disk drive, a tape drive, etc. The storage 1008 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 1000 may include a program logic 1010 including code 1012 that may be loaded into the memory 1006 and executed by the processor 1004 or circuitry 1002. In certain embodiments, the program logic 1010 including code 1012 may be stored in the storage 1008. In certain other embodiments, the program logic 1010 may be implemented in the circuitry 1002. Therefore, while FIG. 10 shows the program logic 1010 separately from the other elements, the program logic 1010 may be implemented in the memory 1006 and/or the circuitry 1002. The system 1000 may also include a display 1014 (e.g., an liquid crystal display (LCD), a light emitting diode (LED) display, a cathode ray tube (CRT) display, a touchscreen display, or any other suitable display). The system 1000 may also include one or more input devices 1016, such as, a keyboard, a mouse, a joystick, a trackpad, or any other suitable input devices). Other components or devices beyond those shown in FIG. 10 may also be found in the system 1000.\nCertain embodiments may be directed to a method for deploying computing instruction by a person or automated processing integrating computer-readable code into a computing system, wherein the code in combination with the computing system is enabled to perform the operations of the described embodiments.\nThe terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments” unless expressly specified otherwise.\nThe terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.\nThe enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.\nThe terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.\nDevices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.\nA description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments.\nFurther, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously.\nWhen a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments need not include the device itself.\nAt least certain operations that may have been illustrated in the figures show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.\nThe foregoing description of various embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.\nEXAMPLES\nThe following examples pertain to further embodiments.\nExample 1 is a method for improving bandwidth of a storage device, wherein the method comprises determining that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media; copying a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; concurrently with the copying of the first subset of the plurality of pages, copying a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; and determining that the copying of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copying of the first subset of the plurality of pages and the second subset of the plurality of pages.\nIn example 2, the subject matter of example 1 may include that the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein copying of the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media comprises: copying the fourth page from the first type of storage media to the second type of storage media, in response to determining that the third page has already been copied from the first type of storage media to the second type of storage media.\nIn example 3, the subject matter of example 1 may include copying the data from the first type of storage media to a set of latches of the non-volatile memory; subsequent to copying the data from the first type of storage media to the set of latches of the non-volatile memory, copying the data from the set of latches to the second type of storage media via operations comprising: switching from a first mode to a second mode using a first set feature command; issuing a second feature set command to specify a destination write mode; and issuing a program opcode to program the second type of storage media.\nIn example 4, the subject matter of example 1 may include issuing a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and issuing a program opcode to program the second type of storage media.\nIn example 5, the subject matter of example 1 may include that the data is moved from the first type of storage media to the second type of storage media without generating an intermediate copy outside of the non-volatile memory.\nIn example 6, the subject matter of example 1 may include that on an average, I/O operations to the first type of storage media are performed faster in comparison to I/O operations to the second type of storage media, wherein the non-volatile memory has fewer blocks configured as the first type of storage media in comparison to the second type of storage media, and wherein data has to be moved periodically from the first type of storage media to the second type of storage media to conserve space in the first type of storage media.\nIn example 7, the subject matter of example 1 may include that the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is quad-level cell (QLC) NAND.\nIn example 8, the subject matter of example 1 may include that the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is multi-level cell (MLC) NAND.\nExample 9 is a non-volatile memory device for improving bandwidth of a storage device, wherein the non-volatile memory device is comprised of a non-volatile memory; and a controller coupled to the non-volatile memory, wherein the controller is operable to: determine that data has to be moved internally within the non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media; copy a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; copy a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media, concurrently with the copy of the first subset of the plurality of pages; and determine that the copy of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copy of the first subset of the plurality of pages and the second subset of the plurality of pages.\nIn example 10, the subject matter of example 9 may include the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein the controller to copy the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media is to: copy the fourth page from the first type of storage media to the second type of storage media, in response to a determination that the third page has already been copied from the first type of storage media to the second type of storage media.\nIn example 11, the subject matter of example 9 may include that the controller is further operable to: copy the data from the first type of storage media to a set of latches of the non-volatile memory; subsequent to the copy of the data from the first type of storage media to the set of latches of the non-volatile memory, copy the data from the set of latches to the second type of storage media via operations performed to: switch from a first mode to a second mode using a first set feature command; issue a second feature set command to specify a destination write mode; and issue a program opcode to program the second type of storage media.\nIn example 12, the subject matter of example 9 may include that the controller is further operable to: issue a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and issue a program opcode to program the second type of storage media.\nIn example 13, the subject matter of example 9 may include that the controller is further operable to: cause the data to be moved from the first type of storage media to the second type of storage media without generation of an intermediate copy outside of the non-volatile memory.\nIn example 14, the subject matter of example 9 may include that on an average, I/O operations to the first type of storage media are performed faster in comparison to I/O operations to the second type of storage media, wherein the non-volatile memory has fewer blocks configured as the first type of storage media in comparison to the second type of storage media, and wherein data has to be moved periodically from the first type of storage media to the second type of storage media to conserve space in the first type of storage media.\nIn example 15, the subject matter of example 9 may include that the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is quad-level cell (QLC) NAND.\nIn example 16, the subject matter of example 9 may include that the first type of storage media is single-level cell (SLC) NAND, wherein the second type of storage media is multi-level cell (MLC) NAND.\nExample 17 is a system for improving bandwidth of a storage device, wherein the system comprises a display; a non-volatile memory device comprising a non-volatile memory; and a controller coupled to the non-volatile memory, wherein the controller is operable to: determine that data has to be moved internally within the non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media; copy a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; copy a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media, concurrently with the copy of the first subset of the plurality of pages; and determine that the copy of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copy of the first subset of the plurality of pages and the second subset of the plurality of pages.\nIn example 18, the subject matter of example 17 may include that the plurality of pages comprise a first page, a second page, a third page and a fourth page, wherein the first subset is the first page, the second page and the third page, wherein the second subset is the fourth page, and wherein the controller to copy the second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media is to: copy the fourth page from the first type of storage media to the second type of storage media, in response to a determination that the third page has already been copied from the first type of storage media to the second type of storage media.\nIn example 19, the subject matter of example 17 may include that the controller is further operable to: copy the data from the first type of storage media to a set of latches of the non-volatile memory; subsequent to the copy of the data from the first type of storage media to the set of latches of the non-volatile memory, copy the data from the set of latches to the second type of storage media via operations performed to: switch from a first mode to a second mode using a first set feature command; issue a second feature set command to specify a destination write mode; and issue a program opcode to program the second type of storage media.\nIn example 20, the subject matter of example 17 may include that the controller is further operable to: issue a feature set command to specify a source address comprising a block number and a page of the first type of storage media and a write mode for a destination address comprising a block number and a page of the second type of storage media; and issue a program opcode to program the second type of storage media.\nIn example 21, the subject matter of example 17 may include that the controller is further operable to: cause the data to be moved from the first type of storage media to the second type of storage media without generation of an intermediate copy outside of the non-volatile memory.\nIn example 22, the subject matter of example 17 may include that on an average, I/O operations to the first type of storage media are performed faster in comparison to I/O operations to the second type of storage media, wherein the non-volatile memory has fewer blocks configured as the first type of storage media in comparison to the second type of storage media, and wherein data has to be moved periodically from the first type of storage media to the second type of storage media to conserve space in the first type of storage media.\nIn example 23, the subject matter of example 17 may include that the first type of storage media is single-level cell (SLC) NAND, and wherein the second type of storage media is quad-level cell (QLC) NAND.\nIn example 24, the subject matter of example 17 may include that the first type of storage media is single-level cell (SLC) NAND, wherein the second type of storage media is multi-level cell (MLC) NAND.\nExample 25 is a system for improving bandwidth of a storage device, wherein the system comprises: means for determining that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media; means for copying a first subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; means for concurrently with the copying of the first subset of the plurality of pages, copying a second subset of the plurality of pages from the first type of storage media to the page of the second type of storage media; and means for determining that the copying of the data from the first type of storage media to the second type of storage media has completed, in response to completion of the copying of the first subset of the plurality of pages and the second subset of the plurality of pages.\nAll optional features of any of the systems and/or apparatus described above may also be implemented with respect to the method or process described above, and specifics in the examples may be used anywhere in one or more embodiments. Additionally, all optional features of the method or process described above may also be implemented with respect to any of the system and/or apparatus described above, and specifics in the examples may be used anywhere in one or more embodiments." } ], "pdf": "https://api.ipscreener.com/v3/pdf/US-2019102102-A1" }, { "relevance": { "score": 204.14038, "position": 2, "country": "US", "number": "9927975", "kind-code": "B2", "family-number": 61071468, "publication-date": "2018-02-08" }, "bibliographic": { "applicant": [ { "name": "Micron Technology" }, { "name": " Inc." } ], "inventor": [ { "name": "Pratt Thomas L." } ], "class": [ { "sub": "G06F3/0604", "type": "CPC" }, { "sub": "G06F3/0605", "type": "CPC" }, { "sub": "G06F3/0634", "type": "CPC" }, { "sub": "G06F3/068", "type": "CPC" }, { "sub": "G06F12/0246", "type": "CPC" }, { "sub": "G06F12/0866", "type": "CPC" }, { "sub": "G06F12/0873", "type": "CPC" }, { "sub": "G06F2212/217", "type": "CPC" }, { "sub": "G06F2212/222", "type": "CPC" }, { "sub": "G06F2212/261", "type": "CPC" }, { "sub": "G06F2212/281", "type": "CPC" }, { "sub": "G06F2212/305", "type": "CPC" }, { "sub": "G06F2212/313", "type": "CPC" }, { "sub": "G06F2212/466", "type": "CPC" }, { "sub": "Y02D10/13", "type": "CPC" }, { "sub": "G06F12/00", "type": "IPC" }, { "sub": "G06F3/06", "type": "IPC" }, { "sub": "G06F12/02", "type": "IPC" }, { "sub": "G06F12/0873", "type": "IPC" } ], "title": [ { "language": "en", "text": "Hybrid memory drives, computer system, and related method for operating a multi-mode hybrid drive" } ], "abstract": [ { "language": "en", "text": "A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. A method of operating a multi-mode hybrid drive may also comprise monitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device, operating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present, and operating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present. Additional hybrid memory drives and computer systems are also described." } ] }, "passage": { "section": "description", "language": "en", "text": "TECHNICAL FIELD\nThe disclosure, in various embodiments, relates generally to the field of computer systems and mass storage devices. More specifically, the disclosure relates to mass storage devices configured to operate as either a hybrid drive or a stand-alone drive depending on its mode of operation.\nBACKGROUND\nNon-volatile memory is commonly used for mass storage of data, such as within consumer electronic devices. Various types of mass storage devices are currently in use, such as solid state devices (SSDs), hard disk drives (HDDs), and hybrid drives. SSDs use solid state memory devices (e.g., Flash memory), which can have advantages over the traditional electro-mechanical magnetic HDDs due to fast data access times, low power consumption, and no moving mechanical parts. As a result, SSDs have been a popular data storage device for the PC and notebook markets. SSDs, however, are more expensive to produce than HDDs. Thus, HDDs are often the drive of choice when large storage is desired" }, "claim": [ { "language": "en", "text": "1. A hybrid memory drive, comprising:\na bulk memory device including:\nbulk storage media including non-volatile memory;\na cache port; and\na first controller operably coupled with the cache port and the bulk storage media; and\na removable cache memory device including:\ncache storage media including non-volatile memory; and\na second controller operably coupled with the cache storage media,\nwherein the first controller is configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being at least one of coupled with the cache port of the bulk memory device or valid for use as a cache for the bulk memory device to operate as a hybrid drive.\n2. The hybrid memory drive of claim 1, wherein the bulk storage media is configured as a hard disk drive.\n3. The hybrid memory drive of claim 1, wherein the bulk storage media is configured as a solid state drive.\n4. The hybrid memory drive of claim 1, wherein the second controller is configured to manage media accesses to the cache storage device responsive to commands received from the first controller when the removable cache memory device is coupled to the cache port.\n5. The hybrid memory drive of claim 1, wherein the bulk memory device is coupled with a host via a first bus selected from the group consisting of a Peripheral Component Interconnect Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a Serial-attached SCSI (SAS) bus, and a Universal Serial Bus (USB).\n6. The hybrid memory drive of claim 5, wherein the bulk memory device is coupled with the removable cache memory device via a second bus selected from the group consisting of a Peripheral Component Interconnect Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a Serial-attached SCSI (SAS) bus, and a Universal Serial Bus (USB).\n7. The hybrid memory drive of claim 6, wherein the first bus and the second bus are of the same bus type.\n8. The hybrid memory drive of claim 6, wherein the first bus and the second bus are of a different bus type, and the first controller is further configured to translate communications between the host and the removable cache memory device using different communication protocols.\n9. The hybrid memory device of claim 1, wherein the bulk storage media include non-volatile memory of a first type, and the cache storage media include non-volatile memory of a second type that is faster than the first type.\n10. A non-volatile memory drive, comprising:\nbulk storage media including physical blocks of non-volatile memory;\na cache port; and\na controller operably coupled with the bulk storage media and the cache port, and configured to:\ndetect whether a removable cache memory device having non-volatile memory is coupled with the cache port; and\noperate the non-volatile memory drive to use the removable cache memory device as a data cache during at least one of a read or write operation responsive to detecting the removable cache memory device is at least one of coupled or valid for use in with the bulk storage media as a hybrid drive.\n11. The non-volatile memory drive of claim 10, wherein the controller is further configured to operate the non-volatile memory drive to use the bulk storage media as a stand-alone drive responsive to detecting the removable cache memory device to not be coupled with the cache port or not valid for use with the bulk storage media.\n12. The non-volatile memory drive of claim 10, wherein the bulk storage media includes solid state storage media.\n13. The non-volatile memory drive of claim 10, wherein the bulk storage media includes magnetic storage media.\n14. The non-volatile memory drive of claim 10, wherein the controller is configured to translate communications with an external host using a first protocol and to communicate with the removable cache memory device using a second protocol.\n15. The non-volatile memory drive of claim 10, wherein the cache port includes a slot configured to receive the removable cache memory device inserted therein.\n16. A method of operating a multi-mode hybrid drive, the method comprising:\nmonitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device;\noperating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present; and\noperating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present.\n17. The method of claim 16, wherein monitoring the cache port is initiated responsive to a power up of the bulk memory device.\n18. The method of claim 16, further comprising:\ndetermining if the removable cache memory device is valid;\noperating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not valid; and\noperating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is valid.\n19. The method of claim 18, wherein determining if the cache memory device is valid includes interrogating the removable cache memory device to determine operational parameters of the removable cache memory device.\n20. The method of claim 19, wherein the operational parameters include at least one of a capacity, a memory type, endurance, or a speed of the removable cache memory device.\n21. The method of claim 19, wherein determining if the cache memory device is valid further includes determining if one or more of the operational parameters falls outside of a predetermined range.\n22. A computer system, comprising:\na chipset; and\na multi-mode hybrid drive operably coupled with the chipset, the multi-mode hybrid drive configured to enable a stand-alone mode for the multi-mode hybrid drive responsive to a removable cache memory device not being coupled to a cache port of the multi-mode hybrid drive, and to enable a hybrid mode for the multi-mode hybrid drive responsive to the removable cache memory device being coupled to a cache port of the multi-mode hybrid drive.\n23. The computer system of claim 22, further comprising:\na processor operably coupled with the chipset;\na graphics processor operably coupled with the chipset and a display; and\nI/O devices operably coupled with the chipset.\n24. The computer system of claim 22, wherein the chipset is operably coupled with the multi-mode hybrid drive via at least one of a Peripheral Component Interconnect Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, and a Serial-attached SCSI (SAS) bus.\n25. The computer system of claim 22, further comprising one of a desktop computer, a laptop computer, a tablet computer, a server, an electronic reader, a communication device, or a computing system incorporating the chipset and the multi-mode hybrid drive." } ], "description": [ { "language": "en", "text": "TECHNICAL FIELD\nThe disclosure, in various embodiments, relates generally to the field of computer systems and mass storage devices. More specifically, the disclosure relates to mass storage devices configured to operate as either a hybrid drive or a stand-alone drive depending on its mode of operation.\nBACKGROUND\nNon-volatile memory is commonly used for mass storage of data, such as within consumer electronic devices. Various types of mass storage devices are currently in use, such as solid state devices (SSDs), hard disk drives (HDDs), and hybrid drives. SSDs use solid state memory devices (e.g., Flash memory), which can have advantages over the traditional electro-mechanical magnetic HDDs due to fast data access times, low power consumption, and no moving mechanical parts. As a result, SSDs have been a popular data storage device for the PC and notebook markets. SSDs, however, are more expensive to produce than HDDs. Thus, HDDs are often the drive of choice when large storage is desired at a lower price.\nHybrid drives include features of both the SSDs and HDDs in that traditional magnetic HDD storage media is used for long term storage and solid state Flash-type storage media is used for cache storage. Thus, hybrid drives have become desirable because they deliver higher performance than conventional drives, but at a more reasonable cost. For example, a hybrid drive can bring more SSD-like performance with the inclusion of Flash memory, but retain the high capacity and some of the lower cost associated with an HDD. As a result, the small amount of solid state memory used in the hybrid drive may result in lower boot times and data access times as well as power savings, but conventional hybrid drives may also limit flexibility in solid state media capacity and add significant complexity for the system manufacturer where multiple hybrid capacity offerings are desired. Because conventional hybrid drives may add complexity to the overall offerings for original equipment manufacturers (OEMs), OEMs may simply offer a smaller set of drive types for consumers to choose from. This same complexity of offerings may exist at the HDD or hybrid drive manufacturer, limiting the number of drive types they may offer as well.\nBRIEF DESCRIPTION OF THE DRAWINGS\nFIG. 1 is a simplified block diagram of a computer system according to an embodiment of the present disclosure.\nFIG. 2 is a simplified block diagram of the hybrid drive of FIG. 1.\nFIG. 3 is a flowchart illustrating a method of operating a bulk memory device as either a stand-alone drive or a hybrid drive according to an embodiment of the present disclosure.\nDETAILED DESCRIPTION\nIn the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is illustrated specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the disclosure. It should be understood, however, that the detailed description and the specific examples, while indicating examples of embodiments of the disclosure, are given by way of illustration only and not by way of limitation. From this disclosure, various substitutions, modifications, additions, rearrangements, or combinations thereof within the scope of the disclosure may be made and will become apparent to those of ordinary skill in the art.\nThe illustrations presented herein are not meant to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely idealized representations that are employed to describe various embodiments of the disclosure. Accordingly, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or all operations of a particular method. In addition, like reference numerals may be used to denote like features throughout the specification and figures.\nInformation and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal for clarity of presentation and description. It will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, wherein the bus may have a variety of bit widths and the disclosure may be implemented on any number of data signals including a single data signal.\nThe various illustrative logical blocks, modules, circuits, and algorithm acts described in connection with embodiments disclosed herein may be implemented or performed with a general-purpose processor, a special-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.\nA processor herein may be any processor, controller, microcontroller, or state machine suitable for carrying out processes of the disclosure. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. When configured according to embodiments of the disclosure, a special-purpose computer improves the function of a computer because, absent the disclosure, the computer would not be able to carry out the processes of the disclosure. The disclosure also provides meaningful limitations in one or more particular technical environments that go beyond an abstract idea. For example, embodiments of the disclosure provide improvements in the technical field of memory devices, particularly for hybrid drives being configured to operate in either a stand-alone mode or a hybrid mode. Embodiments include features that improve the functionality of the hybrid drive such that a new device and method for operating the hybrid drive are described.\nIn addition, it is noted that the embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts can be performed in another sequence, in parallel, or substantially concurrently. In addition, the order of the acts may be re-arranged. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, interfacing with an operating system, etc. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions (e.g., software code, firmware, etc.) on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.\nEmbodiments of the present disclosure include a computer system comprising a chipset and a multi-mode hybrid drive operably coupled with the chipset. In some embodiments, the multi-mode hybrid drive is configured to enable a stand-alone mode for the multi-mode hybrid drive responsive to a removable cache memory device not being coupled to a cache port of the multi-mode hybrid drive, and to enable a hybrid mode for the multi-mode hybrid drive responsive to the removable cache memory device being coupled to a cache port of the multi-mode hybrid drive. As used herein, the term “cache port” does not denote any particular required physical structure for coupling a removable cache memory. In addition, the term “cache” is used for convenience to refer to a common usage of a hybrid drive being as a temporary cache of data storage that may be duplicated in the main storage area. In some embodiments, however, it is contemplated that the data stored in the cache may not be duplicated in the main storage area. In such an embodiment, the cache memory device may be considered a different tier of storage from the main storage area such that data in the cache memory device may not necessarily be duplicated in the main storage area or may be temporary in nature.\nFIG. 1 is a simplified block diagram of a computer system 100 according to an embodiment of the present disclosure. The computer system 100 may be a consumer electronic device, such as a desktop computer, a laptop computer, a tablet computer, an electronic reader, a smart phone or other type of communication device, as well as any type of computing system (e.g., a server) incorporating non-volatile storage.\nThe computer system 100 includes a chipset 102 (also referred to as a “host”) that includes one or more memory controller hubs 104, 106. In particular, the chipset 102 may include a memory controller hub 104 (also referred to as a “northbridge”) and an I/O controller hub 106 (also referred to as a “southbridge”). The memory controller hubs 104, 106 may include one or more processors (e.g., single core, multi-core, etc.). Of course, some embodiments may include an integrated chipset that incorporates the features of the northbridge/southbridge configuration into a single integrated circuit having a single processor die.\nThe computer system 100 may also include different devices and ports coupled with the chipset 102 through different communication buses. For example, the memory controller hub 104 may be coupled with a processor 108, volatile memory 112, a graphics processor 122, and a display 124. The processor 108 may be the central processing unit (CPU) for the computer system 100. The volatile memory 112 may include random-access memory (RAM) that may also be referred to as “system memory” (e.g., DRAM, SDRAM, LPDDR, etc.). The graphics processor 122 is configured to handle a variety of multimedia tasks responsive to receiving data from the chipset 102 to provide the video display signals to the display 124. The memory controller hub 104 is configured to enable the processor 108, the volatile memory 112, the graphics processor 122 to communicate with each other, as well as to communicate with the devices and ports coupled with the I/O controller hub 106.\nThe I/O controller hub 106 may be coupled with a hybrid drive 110, as well as other I/O devices and ports such as a super I/O controller 114 and I/O devices 116, USB ports 118, and other network interfaces 120. Of course, it is recognized that the computer system 100 shown in FIG. 1 is a simplified configuration. Other resources and devices may also be included as desired, such as an optical drive (e.g., DVD, BLU-RAY®, etc.). In addition, some components shown as separate may exist in an integrated package or be integrated in a common integrated circuit with other components. Systems may also include a variety of components, including parallel (e.g., redundant) resources. The hybrid drive 110 may be a multi-mode drive that is configured to operate in either a stand-alone mode or a hybrid mode, which will be discussed further below with reference to FIGS. 2 and 3.\nIn some embodiments, a hybrid memory drive comprises a bulk memory device and a removable cache memory device. The bulk memory device includes bulk storage media, a cache port, and a first controller operably coupled with the cache port and the bulk storage media. The bulk storage media includes non-volatile memory. The removable cache memory device includes cache storage media including non-volatile memory and a second controller operably coupled with the cache storage media. The first controller is configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being at least one of coupled with the cache port of the bulk memory device or valid for use as a cache for the bulk memory device to operate as a hybrid drive.\nIn some embodiments, a non-volatile memory drive comprises bulk storage media including physical blocks of non-volatile memory, a cache port, and a controller operably coupled with the bulk storage media and the cache port. The controller is configured to detect whether a removable cache memory device having non-volatile memory is coupled with the cache port, and operate the non-volatile memory drive to use the removable cache memory device as a data cache during at least one of a read or write operation responsive to detecting the removable cache memory device is at least one of coupled or valid for use in with the bulk storage media as a hybrid drive.\nThe hybrid drive 110 may be coupled with the I/O controller hub 106 using a serial or parallel data bus. For example, the data bus from the hybrid drive 110 to the chipset 102 may include a Peripheral Component Interconnect Express (PCIe) bus, Serial Advanced Technology Attachment (SATA) bus, Parallel Advanced Technology Attachment (PATA) bus, Small Computer System Interface (SCSI) bus, Serial-attached SCSI (SAS) bus, a Universal Serial Bus (USB), or combinations thereof.\nFIG. 2 is a simplified block diagram of the hybrid drive 110 of FIG. 1. The hybrid drive 110 includes a bulk memory device 200 and a removable cache memory device 210. The bulk memory device 200 may be configured to operate in either a stand-alone mode or a hybrid mode responsive to detecting the presence of the removable cache memory device 210 being coupled with the bulk memory device 200. For example, the bulk memory device 200 may be configured to operate in the stand-alone mode if the removable cache memory device 210 is not coupled with the bulk memory device 200, and in the hybrid mode if the removable cache memory device 210 is coupled with the bulk memory device 200.\nThe bulk memory device 200 may include a first controller 202, bulk storage media 204, and a cache port 206. The first controller 202 of the bulk memory device 200 may be coupled with the I/O controller hub 106 via a first bus 201. The first controller 202 of the bulk memory device 200 may be coupled with the bulk storage media 204 via a second bus 203. The first controller 202 of the bulk memory device 200 may be coupled with the cache port 206 via a third bus 205.\nThe bulk storage media 204 may include non-volatile memory. Embodiments of the present disclosure include non-volatile memory arrays of a variety of different configurations and capacity. In some embodiments, the non-volatile memory may be configured as an HDD, as an SSD, or as another suitable type of long term data storage. In some embodiments, the HDD may include magnetic media. In some embodiments, the bulk storage media 204 may be configured as solid state media (e.g., an SSD). The solid state media may include memory such as Flash-based memory (e.g., NAND Flash), which may include blocks of single-level cells (SLC), multi-level cells (MLC) (e.g., triple-level cells (TLC), quad-level cells (QLC), etc.), or combinations thereof.\nThe removable cache memory device 210 may include a second controller 212 operably coupled with cache storage media 214. The cache storage media 214 may also include non-volatile memory. In some embodiments, the non-volatile memory of the cache storage media 214 may be configured with solid state media, such as Flash-based memory (e.g., NAND Flash) or 3D XPoint. In some embodiments, the removable cache memory device 210 may be configured as a secure digital (SD) card, a CFX card, or as a card that employs other non-volatile memory technologies having an embedded controller. The second controller 212 may be configured to perform the media management functions (e.g., read/write) for the removable cache memory device 210 responsive to commands received from the bulk memory device 200.\nThe cache port 206 may, optionally, be integrated (e.g., as a slot, a port, etc.) with the form factor of the bulk memory device 200 such that the removable cache memory device 210 may be inserted into the cache port 206 to transform the bulk memory device 200 into a hybrid drive. In some embodiments, the cache port 206 may be exposed to an outside of the form factor (e.g., box) of the memory device 210. When connected, the bulk memory device 200 and the removable cache memory device 210 may be essentially a single unit, which may enable the drive manufacturer and/or OEM to determine whether the drive for a particular product should be a stand-alone drive or a hybrid drive. In addition, the drive manufacturer and/or OEM may determine the capacity of the hybrid drive by mixing and matching bulk memory devices 200 with removable cache memory devices 210 having the desired combination of bulk storage capacity and cache storage capacity while maintaining a common form factor.\nThe bulk memory device 200 includes firmware (e.g., stored in the bulk storage media 204 or other memory) configured to detect the presence of the removable cache memory device 210 and cause the first controller 202 to reconfigure the operation of the bulk memory device 200 in either a stand-alone mode or a hybrid mode depending on the presence of the removable cache memory device 210 in the cache port 206. As a result, the bulk memory device 200 may run the software to operate as either a stand-alone drive or a hybrid drive to determine where data is stored and retrieved during operation. Thus, the host may not need to have its software reconfigured, which may result in a simpler implementation for the OEM and/or the drive manufacturer when assembling the hybrid drive. In addition, because the removable cache memory device 210 has its own controller (i.e., second controller 212) configured to perform the media management functions for the removable cache memory device 210, the firmware of the bulk memory device 200 may be simplified in hybrid mode as the built-in firmware on the removable cache memory device 210 may already be able to perform the cache functions responsive to receiving commands from the bulk memory device 200.\nThe buses 201, 205 coupling the first controller 202 to the external devices (e.g., chipset 102 (FIG. 1), removable cache memory device 210) may be configured with one or more different interface configurations, such as PCIe, SATA, PATA, SCSI, SAS, or combinations thereof. Other interface configurations and protocols are also contemplated. In some embodiments, the first bus 201 and the third bus 205 may be configured according to the same type of interface and communicate via the same protocol. For example, both the first bus 201 and the third bus 205 may be configured as a PCIe bus and the first controller 202 may be configured to communicate using a non-volatile memory express (NVME) protocol. In some embodiments, the first bus 201 and the third bus 205 may be configured according to a different type of interface and communicate via a different protocol. For example, the first bus 201 may be configured as a SATA bus for the first controller 202 to communicate with the I/O controller hub 106, and the third bus 205 may be configured as a PCIe bus for the first controller 202 to communicate with the removable cache memory device 210. In such an embodiment, the first controller 202 may be configured to perform a translation between the different protocols used to communicate over the different interfaces.\nIn order for the cache storage media 214 to be used to cache data during operation to speed up the operation of the hybrid drive 110, the cache storage media 214 may be configured with faster memory than the bulk storage media 204. In such an embodiment, a suitable NAND-based Flash device may be used as the removable cache memory device 210 in combination with an HDD drive including the internal bulk storage media. Many NAND-based Flash devices are faster than an HDD drive, which means that many NAND-based Flash devices may provide a valid combination with the HDD drive to improve its speed with the removable cache memory device 210. In another embodiment, a suitable NAND, 3D Xpoint, or other non-volatile memory based device may be used as the removable cache memory device 210 in combination with an SSD drive including the internal bulk storage media. Some NAND-based Flash devices may be slower than an SSD drive depending on the specific type of memory used in each. As a result, using slower memory as the removable cache memory device 210 in comparison to the bulk memory device 200 may not actually improve performance relative to just using the bulk storage media 204 for both bulk storage and cache storage. Thus, the storage controller 202 may determine that the specific combination of the bulk memory device 200 with the removable cache memory device 210 is invalid. Similarly, the storage controller 202 may determine that the storage media in the removable cache device 210 has other characteristics (e.g., capacity, endurance) that make it unsuitable for use as a cache for the bulk memory device 200, and determine the combination invalid.\nEmbodiments of the present disclosure also include methods of operating a multi-mode hybrid drive. Such a method may comprise monitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device, operating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present, and operating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present and valid.\nFIG. 3 is a flowchart 300 illustrating a method of operating a bulk memory device as either a stand-alone drive or a hybrid drive according to an embodiment of the present disclosure. At operation 310, the bulk memory device may monitor the cache port. As discussed above, the cache port may be integrally formed within the form factor of the bulk memory device to receive a removable cache device inserted therein. Such monitoring may be initiated at power up of the bulk memory device as well as throughout operation of the bulk memory device.\nAt operation 320, the bulk memory device may determine if the removable cache memory device is present in the cache port. If not, the stand-alone mode of the bulk memory device may be enabled at operation 330, and the bulk memory device may continue to monitor the cache port until a removable cache memory device is present. During stand-alone mode, data accesses (e.g., read/write) may be performed in the bulk storage media of the bulk memory device only.\nAt operation 340, the bulk memory device may interrogate the cache memory device. For example, the first controller of the bulk memory device may talk with the second controller of the removable cache memory device to determine operational parameters (e.g., capacity, type, endurance, speed, etc.) of the removable cache memory.\nAt operation 350, the bulk memory device may determine if the removable cache memory device is valid for the intended usage scenario. For example, the bulk memory device may determine if the type of memory is compatible with the controller of the bulk memory device. The bulk memory device may also determine if the capacity, endurance, and/or speed is above a desired threshold and/or within a desired range of operation. For example, if the speed of the removable cache memory device is slower than the speed of the bulk memory device, then the bulk memory device may be better off operating in its stand-alone mode because using the removable cache memory device to cache data in hybrid mode may not improve performance. Similarly, if the capacity of the removable cache memory device is below a predetermined threshold for its intended use, then the bulk memory device may be better off operating in its stand-alone mode.\nAt operation 360, the bulk memory device determines that the removable cache memory device is valid for the intended use case, the hybrid mode may be enabled. As a result, the first controller of the bulk memory device may coordinate data accesses between the removable cache memory device and/or the internal bulk storage media. For example, if a read operation is received from the host, the first controller may determine if the requested data is available in the removable cache memory device. If so, the first controller may retrieve the requested data from the removable cache memory device. If the requested data is not available in the removable cache memory device, the first controller may retrieve the requested data from the internal bulk storage media. In some embodiments, the first controller may also store (e.g., move, copy, etc.) the requested data from the internal bulk storage media into the removable cache memory device for future access. If a write operation is received from the host, the first controller may determine where the incoming data should be stored (e.g., in the removable cache memory device, the bulk storage media, or both). Such a determination may depend on the priority given to certain data types according to the firmware of the bulk memory device when operating in hybrid mode. In some embodiments, the first controller may perform a garbage collection process to move data from the removable cache memory device to the internal bulk storage media after a predetermined period has elapsed without use of the hybrid drive and/or during which data stored in the removable cache memory device has not been accessed. At any point in the process, a notification may be issued to the host if the bulk memory device detects the removal of the removable storage device from the bulk memory device.\nWhile the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents." } ], "pdf": "https://api.ipscreener.com/v3/pdf/US-9927975-B2" } ] } } }

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